The Designer's Guide to VHDL, 2nd Edition

Peter J. Ashenden


Source Code and Test Benches

Source code directories

Zip archive of source code

Compressed tar archive of sources

There is a separate directory for each chapter, with the directory named ch_cc containing the files for Chapter cc. In addition the directory named ap_a contains files for Appendix A. Within each directory (except those for the four case study chapters) the files are named using the following scheme:

The naming of files for the case studies varies from this scheme and is typical of schemes that might be used for real design projects. The file names are based on the VHDL design units they contain. The scheme is: The directory named util contains a VHDL package called stimulus_generators, which should be analysed into a library called util for use in some of the test benches. The package provides procedures to generate all possible stimulus values for vector inputs of various types.

In many of the code examples in the book, segments of code are elided, indicated by ellipsis points (...). Their treatment in the source code files varies, depending on the reason for elision. If the code is elided for brevity, the code is included in full in the file. If the code is elided because it is not relevant to the example, it is also elided in the file. The file contains the ellipsis points commented out. If the elision results in syntactically incorrect code, "fix-up" code may be inserted to allow the file to be analyzed without error. In some cases, test-bench code may also be inserted.


If you have comments, please send me email at peter@ashenden.com.au. Thanks.