The Designer's Guide to VHDL, 2nd Edition

Peter J. Ashenden


Errata

If you detect an error that is not on the list below, I would be pleased to hear about it. You can send email to me at peter@ashenden.com.au.

Thanks.

You can check which printing you have by looking on the copyright page (page iv) in the front matter of the book. Under the line "Printed in the United States of America" there is a line with two groups of numbers. The first group of two-digit numbers represents the years of printing, with the rightmost being the year of the printing you are reading. The second group represents the printing number, with the rightmost being the printing you are reading.

If the rightmost single digit is 1 or 2, then you should read both the Corrections to the first and second printings and the Corrections to the third and subsequent printings.

If the rightmost single digit is 3 or greater, then you should read only the Corrections to the third and subsequent printings.


Corrections to the first and second printings

Page 14: In the caption of Figure 1-13, replace "modell" with "model".

Page 16, Figure 1-14: In the diagram, port d of component bit1 should be connected to port d1 of the enclosing entity, and port clk of component bit should be connected to the signal int_clk.

Page 17: In the 2nd line of the Lexical Elements section, delete the comma after "strings".

Page 63: In the 1st line after the second code block, replace "operand" with "opcode".

Page 94: In the 1st line of Section 4.2, replace "section" with "chapter".

Page 94: In the 8th line from the bottom, replace "short_sample" with "short_sample_buf".

Page 144: In the 3rd line after Figure 5-27, replace "reg4" with "counter".

Page 160: In the 7th line of the code block in Exercise 22, replace "data_read" with "data_ready".

Page 244: In the 6th line of the Exampe, replace "tmp" with "tmp1".

Page 255: In the caption of Figure 8-17, replace "math_real" with "math_complex".

Page 325: In the 2nd line from the bottom, insert "the" before "counter".

Page 343: In the 1st line, replace "explictly" with "explicitly".

Page 363: In the 9th line of the Example, replace "Figure 149" with "Figure 14-9".

Page 612: In the 1st line of Exercise 8, replace "Lanuage" with "Language".

Page 632: In the caption of Figure 21-7, replace "compute" with "computer".

Page 707: In the answer to Exercise 4 of Chapter 5, replace "s = '1'" with "s = '0'".

Page 708: In the answer to Exercise 11 of Chapter 5, the condition in the assertion statement should be

(not clk'event) or clk'delayed'last_event >= t_pw_clk


Corrections to the third and subsequent printings

Page 374: In the 8th line after the heading "DLX Registers", replace "r2" with "f2".

Page 643: In the first line of the last paragraph (immediately before the code example at the bottom of the page), replace "selected" with "conditional".


Errata in the source code

ch_10/bv_test-bench.vhd: On line 702, change "assert byte = X"10" and div_by_zero;" to "assert div_by_zero;". The reason is that the procedure bv_divu does not assign to the formal parameter bv_quotient in the case of the divisor being zero. Whether the actual parameter, byte, is unchanged or updated with the default initial value of the formal parameter depends on whether the simulator uses reference or value semantics for parameter passing. The LRM allows an implementation to choose either mechanism and deems a model to be erroneous if it depends on the choice. Thus, the assertion in the model in question should not specify whether the value of byte be X"10" or X"00". (Corrected on website 06-Sep-2005.)